1. Field of the Invention
This invention relates in general to the field of application specific integrated circuits (“ASICs”), and more specifically, to simulation and debugging techniques used to filter unknown values.
2. Background of the Invention
Application Specific Integrated Circuits (“ASICs”) are commonly used in various computing functions. Typically, while an ASIC is being designed and before a foundry fabricates it, the ASIC is verified and tested in a simulation environment. After fabrication, the ASIC is tested to perform in real life situations using lab equipment.
ASICs are first designed in a hardware description language (“HDL”) and then synthesized to logical components, like registers flip-flops, AND gates, and OR gates.
Flip-flops are logical sequential elements that store logical digital values, for example, 1 and 0. Inputs to a conventional flip-flop are clock, data and a write enable signals. The clock signal oscillates at a regular interval; data is sampled at the transition of the clock signal and at the assertion of write enable signal. The output of a typical flip-flop is either 1 or 0.
Simulations are typically run using simulators to verify the functionality of an ASIC design. Simulation includes monitoring, forcing, checking and releasing actions using simulator language constructs.
The simulator has the ability to create a logical X (unknown logic level) when inputs to a component (for example, a flip-flop) violate set-up or hold time requirements for the component. These set-up and hold times are often specified to the simulator.
When a simulation fails, different debugging techniques are used to debug the failure mechanisms. One technique is to propagate the X value from a logic element (for example, a flip-flop) to the rest of the ASIC logic elements. This technique works well if the generated X value is based on a true error. However, not all X values are based on true errors. For example, X values originate from a register that is constructed from bits in different clock domains. If the register is not synchronized to both clock domains, then the simulator due to timing violations originates an X value. Such X values are not design related and are propagated to the rest of the design, resulting in an early termination of the simulation process. This is undesirable because it impedes the overall simulation process.
Therefore, what is needed is a method and system to filter localized unwanted X's from the rest of the design, while preserving the global checks that the simulator performs to create X's for legitimate timing violations that should be propagated through the design.